(1) Field of the Invention
The present invention relates to a method of fabricating a DRAM device, and more particularly, to a method of forming a capacitor-under-bit line DRAM device having an enlarged process window in the fabrication of an integrated circuit device.
(2) Description of the Prior Art
Capacitors are critical components in the integrated circuit devices of today. A dynamic random access memory (DRAM) cell typically is composed of a pass transistor (for switching) and a storage capacitor. The state-of-the-art DRAM cell has typically either a stacked capacitor or a trench capacitor; referred to as xe2x80x9cstack cellxe2x80x9d or xe2x80x9ctrench cellxe2x80x9d, respectively. Among stack cells, the capacitor can be fabricated either above or below the bit-line, referred to as Capacitor Over Bit-line (COB) or Capacitor Under Bit-line (CUB) structures. One of the major limitations for scaling down a CUB DRAM is the insufficient accuracy of lithography, especially in the patterning of bit line contacts. Isolation between storage nodes and bit line contacts or isolation between plates and bit line contacts can fail due to mis-alignment issues.
U.S. Pat. No. 6,090,697 to Xing et al and U.S. Pat. No. 5,705,438 to Tseng teach CUB processes. U.S. Pat. No. 6,100,129 to Tu et al discloses a process for making a capacitor. U.S. Pat. No. 5,866,453 to Prall et al teaches another capacitor process.
Accordingly, it is a primary object of the invention to provide an effective and very manufacturable process for fabricating a capacitor-under-bit line (CUB) DRAM device.
Another object of the present invention is to provide a method for fabricating a CUB DRAM device that is resistant to lithography mis-alignment.
A further object is to provide a method for fabricating a CUB DRAM device having a recessed lower electrode.
Yet another object of the invention is to provide a method for fabricating a CUB DRAM device having enlarged top plate openings.
Yet another object is to provide a method for fabricating a CUB DRAM device having an enlarged process window for bit line contact patterning.
In accordance with the objects of this invention, a method for fabricating a CUB DRAM device having an enlarged process window for bit line contact patterning is achieved. A plurality of capacitor node contact junctions and a bit line junction are provided in a semiconductor substrate. A node contact plug is formed through a first insulating layer to each of the capacitor node contact junctions. A bit line contact plug is formed to the bit line junction. A second insulating layer is deposited overlying the node contact plugs. Openings are etched through the second insulating layer to each of the node contact plugs. An polysilicon layer is conformally deposited overlying the second insulating layer and within the openings. The polysilicon layer is recessed below the top of the openings wherein each of the polysilicon layers forms a bottom plate electrode of a capacitor. A capacitor dielectric layer is formed overlying the bottom plate electrodes and the second insulating layer. A polysilicon layer is deposited overlying the capacitor dialectic layer and patterned to form top capacitor plates overlying each of the bottom plate electrodes to complete the capacitors. A third insulating layer is deposited overlying the capacitors. An opening is etched through the third and second insulating layers between the capacitors to the bit line contact plug and filled with a conducting layer to form a bit line to complete fabrication of a DRAM with CUB cell in an integrated circuit device.